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high side switch pna suffix (pb-free) 98arl10596d 24-pin pqfn 35xs3400 ordering information device temperature range (t a ) package mc35xs3400cpna - 40c to 125c 24 pqfn mc35xs3400dpna document number: mc35xs3400 rev. 8.0, 1/2011 freescale semiconductor advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, inc., 2008 - 2011. all rights reserved. quad high side switch (quad 35 mohm) the 35xs3400 is one in a family of devices designed for low-voltage automotive lighting applications. its four low r ds(on) mosfets (quad 35 mohm) can control four separate 28 w bulbs, and/or leds. programming, control and diagnostics are accomplished using a 16-b it spi interface. its output wit h selectable slew-rate improves electromagnetic compatibility (e mc) behavior. additionally, each output has its own parallel input or spi control for pulse-width modulation (pwm) control if desired. the 35xs3400 allows the user to program via the spi the fault current trip levels and duration of acceptable lamp inrush. the device has fail-safe mode to provide fail- safe functionality of the output s in case of mcu damaged. features ? four protected 35 m high side switches (at 25c) ? operating voltage range of 6.0 v to 20 v with standby current < 5.0 a, extended mode from 4.0 v to 28 v ?8.0 mhz 16-bit 3.3 v and 5.0 v spi control and status reporting with dai sy chain capability ? pwm module using external clock or calibratable internal oscill ator with programm able outputs delay management ? smart over-current shutdown, sev ere short-circuit, over- temperature protections with time limited autoretry, and fail-safe mode in case of mcu damage ? output off or on open-load detection compliant to bulbs or leds and short to battery detection. analog current feedback with selectable ratio and board temperature feedback. ? pb-free packaging designated by suffix code dpna mcu 35xs3400 v dd v dd v pwr v dd v pwr wake fs sclk cs so rst si in0 in1 in2 in3 csns fsi gnd vdd vpwr hs0 hs1 hs2 hs3 load i/o sclk cs si i/o so i/o i/o i/o i/o a/d gnd load load load figure 1. 35xs3400 simpli fied application diagram
analog integrated circuit device data 2 freescale semiconductor 35xs3400 device variations device variations table 1. device variations characteristic symbol min typ max unit wake input clamp voltage , cl(wake) < 2.5 ma 35xs3400c 35xs3400d v cl(wake) 18 20 25 27 32 35 v fault detection blanking time 35xs3400c 35xs3400d t fault - - 5.0 5.0 20 10 s output shutdown delay time 35xs3400c 35xs3400d t detect - - 7.0 7.0 30 20 s peak package reflow temperature during reflow (1) , (2) t pprt note 2 c 1. pin soldering temperature limit is for 10 seconds maximum duration. not designed for immersion soldering. exceeding these lim its may cause malfunction or permanent damage to the device. 2. freescale?s package reflow capability me ets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.fr eescale.com, search by part number [e.g. remove prefixes/suffixe s and enter the core id to view all orderable parts (i.e. mc33xxxd enter 33x xx), and review parametrics. i
analog integrated circuit device data freescale semiconductor 3 35xs3400 internal block diagram internal block diagram gnd programmable watchdog over-temperature detection logic severe short-circuit selectable over-current internal regulator selectable slew rate gate driver over/under-voltage protections hs0 vpwr vdd cs sclk so si rst wake fs in0 fsi in3 hs1 hs0 hs1 hs2 hs3 hs2 hs3 in1 in2 detection selectable output csns v reg i dwn i up i dwn r dwn open-load detections detection temperature feedback v reg short to vpwr detection charge v dd failure detection calibratable oscillator pwm module vpwr voltage clamp r dwn current recopy analog mux over-temperature prewarning v dd pump por figure 2. 35xs3400 simplified internal block diagram
analog integrated circuit device data 4 freescale semiconductor 35xs3400 pin connections pin connections transparent top view of package 13 24 12 1098 7654 321 11 23 22 19 20 21 16 17 18 15 14 so gnd hs3 hs1 nc hs0 hs2 gnd fsi vdd si sclk cs rst wake fs in3 in2 nc in1 in0 csns gnd vpwr figure 3. 35xs3400 pin connections table 2. 35xs3400 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 19 . pin number pin name pin function formal name definition 1 csns output output current monitoring this pin reports an analog va lue proportional to the designated hs[0:3] output current or the temperature of the gnd flag (pin 14). it is used externally to generate a ground-referenced voltage for the microcontroller (mcu) . current recopy and temperature fee dback is spi programmable. 2 3 5 6 in0 in1 in2 in3 input direct inputs each direct input controls the device mode . the in[0 : 3] high side input pins are used to directly contr ol hs0 : hs3 high side output pins. the pwm frequency can be generated from in0 pin to pwm module in case the external clock is set. 7 fs output fault status ( active low) this pin is an open drain configured output r equiring an external pull-up resistor to v dd for fault reporting. 8 wake input wake this input pin controls the device mode. 9 rst input reset this input pin is used to initialize t he device configu ration and fault registers, as well as place the device in a low-current sleep mode. 10 cs input chip select ( active low) this input pin is connected to a chip se lect output of a master microcontroller (mcu). 11 sclk input serial clock this input pin is connected to the mcu pr oviding the r equired bit shift clock for spi communication. 12 si input serial input this pin is a command data input pin connected to the spi serial data output of the mcu or to the so pin of the previous device of a daisy - chain of devices.
analog integrated circuit device data freescale semiconductor 5 35xs3400 pin connections 13 vdd power digital drain voltage this pin is an external voltage input pi n used to supply power interfaces to the spi bus. 14, 17, 23 gnd ground ground these pins, internally shorted, are the ground for the logic and analog circuitry of the device. these ground pins must be also shorted in the board. 15 vpwr power positive power supply this pin connects to the positive power supply and is the source of operational power for the device. 16 so output serial output this output pin is connected to the spi serial data input pin of the mcu or to the si pin of the next device of a daisy - chain of devices. 18 19 21 22 hs3 hs1 hs0 hs2 output high side outputs protected 35 m : high side power output pins to the load. 4, 20 nc n/a no connect these pins may not be connected. 24 fsi input fail-safe input this input enables the watchdog timeout feature. table 2. 35xs3400 pin definitions (continued) a functional description of each pin can be found in the functional pin description section beginning on page 19 . pin number pin name pin function formal name definition
analog integrated circuit device data 6 freescale semiconductor 35xs3400 electrical characteristics maximum ratings electrical characteristics maximum ratings table 3. maximum ratings all voltages are with respect to ground unless otherwise no ted . exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings v pwr supply voltage range load dump at 25c (400 ms) maximum operating voltage reverse battery at 25c (2.0 min.) v pwr(ss) 41 28 -18 v v dd supply voltage range v dd -0.3 to 5.5 v input / output voltage (6) -0.3 to v dd + 0.3 v wake input clamp current i cl(wake) 2.5 ma csns input clamp current i cl(csns) 2.5 ma hs [0:3] voltage positive negative v hs[0:3] 41 -16 v output current (3) i hs[0:3] 6 a output clamp energy using single-pulse method (4) e cl [0:3] 35 mj esd voltage (5) human body model (hbm) for hs[0:3], vpwr and gnd human body model (hbm) for other pins charge device model (cdm) corner pins (1, 13, 19, 21) all other pins (2-12, 14-18, 20, 22-24) v esd1 v esd2 v esd3 v esd4 8000 2000 750 500 v thermal ratings operating temperature ambient junction t a t j - 40 to 125 - 40 to 150 c storage temperature t stg - 55 to 150 c thermal resistance thermal resistance (7) junction to case junction to ambient r jc r ja <1.0 30 c/ w peak package reflow temperature during reflow (8) , (9) t pprt note 9 c notes 3. continuous high side output current rating so long as maximum junction temp erature is not exc eeded. calculation of maximum ou tput current using package thermal resistance is required. 4. active clamp energy using single- pulse method (l = 2.0 mh, r l = 0 , v pwr = 14 v, t j = 150 c initial). 5. esd testing is performed in accordance with the human body model (hbm) (c zap = 100 pf, r zap = 1500 ) , the machine model (mm) (c zap = 200 pf, r zap = 0 ), and th e charge device model (cdm), robotic (c zap = 4.0 pf). 6. input / output pins are: in[0:3], rst , fsi, csns, si, sclk, cs , so, fs 7. device mounted on a 2s2p test board per jedec jesd51-2. 15 c/w of r ja can be reached in a real application case (4 layers board). 8. pin soldering temperature limit is for 10 seconds maximum dura tion. not designed for immersion so ldering. exceeding these lim its may cause malfunction or permanent damage to the device. 9. freescale?s package reflow capability m eets p b-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.free scale.com, search by par t number [e.g. remove prefixes/suffixe s and enter the core id to view all orderable parts ( i.e. mc33xxxd enter 33xxx), and review parametrics.
analog integrated circuit device data freescale semiconductor 7 35xs3400 electrical characteristics static electrical characteristics static electrical characteristics table 4. static electric al characteristics characteristics noted under conditions 6.0 v d v pwr d 20 v, 3.0 v d v dd d 5.5 v, - 40 q c d t a d 125 q c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit power inputs battery supply voltage range fully operational extended mode (10) v pwr 6.0 4.0 ? ? 20 28 v battery clamp voltage (11) v pwr(clamp) 41 47 53 v v pwr operating supply current outputs commanded on, hs[0 : 3] open, in[0:3] > v ih i pwr(on) ? 6.5 20 ma v pwr supply current outputs commanded off, off open-load detection disabled, hs[0 : 3] shorted to the ground with v dd = 5.5 v wake > v ih or rst > v ih and in[0:3] < v il i pwr(sby) ? 6.0 8.0 ma sleep state supply current v pwr = 12 v, rst = wake = in[0:3] < v il , hs[0 : 3] shorted to the ground t a = 25c t a = 85c i pwr(sleep) ? ? 1.0 ? 5.0 30 p a v dd supply voltage v dd(on) 3.0 ? 5.5 v v dd supply current at v dd = 5.5 v no spi communication 8.0 mhz spi communication (12) i dd(on) ? ? 1.6 5.0 2.2 ? ma v dd sleep state current at v dd = 5.5 v i dd(sleep) ? ? 5.0 p a over-voltage shutdown threshold v pwr(ov) 28 32 36 v over-voltage shutdown hysteresis v pwr(ovhys) 0.2 0.8 1.5 v under-voltage shutdown threshold (13) v pwr(uv) 3.3 3.9 4.3 v v pwr and v dd power on reset threshold v supply(por) 0.5 ? 0.9 v pwr(uv) v dd supply failure threshold ( for v pwr > v pwr(uv) ) v dd(fail) 2.2 2.5 2.8 v recovery under-voltage threshold v pwr(uv)_up 3.4 4.1 4.5 v outputs hs0 to hs3 output drain-to-source on resistance ( i hs = 2.0 a, t a = 25 q c) v pwr = 4.0 v v pwr = 6.0 v v pwr = 10 v v pwr = 13 v r ds(on)_25 ? ? ? ? ? ? ? ? 100 55 35 35 m : notes 10. in extended mode, the functionality is guaranteed but not the electrical parameters. from 4.0 v to 6.0 v voltage range, the device is only protected with the thermal shutdown detection. 11. measured with the outputs open. 12. typical value guaranteed per design. 13. output will automatically recover with time limited autoretry to instructed state when v pwr voltage is restored to normal as long as the v pwr degradation level did not go below the under-voltage power-on reset th reshold. this applies to all internal device logic that i s supplied by v pwr and assumes that the external v dd supply is within specification.
analog integrated circuit device data 8 freescale semiconductor 35xs3400 electrical characteristics static electrical characteristics outputs hs0 to hs3 (continued) output drain-to-source on resistance (i hs = 2.0 a, t a = 150 q c) v pwr = 4.5 v v pwr = 6.0 v v pwr = 10 v v pwr = 13 v r ds(on)_150 ? ? ? ? ? ? ? ? 170 94 66 66 m : output source-to-drain on resistance (i hs = -2.0 a, v pwr = -18 v ) (14) t a = 25 q c t a = 150 q c r sd(on) ? ? ? ? 52.5 70 m : maximum severe short-circuit impedance detection (15) r short 70 160 200 m : output over-current detection levels (6.0 v < v hs[0:3] < 20 v) ochi1_0 ochi2_0 oc1_0 oc2_0 oc3_0 oc4_0 oclo4_0 oclo3_0 oclo2_0 oclo1_0 39.5 25.2 22 18.9 15.7 12.6 9.4 6.3 5.0 3.2 47 30 26.2 22.5 18.7 15 11.2 7.5 6.0 4.0 54.5 34.8 30.4 26.1 21.7 17.4 13.0 8.7 7.0 4.8 a c sr0 current recopy accuracy with one calibration point (6.0 v < v hs[0:3] < 20 v) (17) output current 2.0 a c sr0_0_acc(cal) -5.0 ? 5.0 % current sense ratio (6.0 v < hs[0:3] < 20 v, csns < 5.0 v) (16) csns_ratio bit = 0 csns_ratio bit = 1 c sr0_0 c sr1_0 ? ? 1/4300 1/25800 ? ? ? current sense ratio (c sr0 ) accuracy (6.0 v < v hs[0:3] < 20 v) output current 6.75 a 2.5 a 1.5 a 0.75 a c sr0_0_acc -12 -13 -16 -20 ? ? ? ? 12 13 16 20 % notes 14. source-drain on resistance (reverse drain-to -source on resistance) with negative polarity v pwr . 15. short-circuit impedance calcul ated from hs[0:3] to gnd pins. value guaranteed per design. 16. current sense ratio = i csns / i hs[0:3] . 17. based on statistical analysis, it is not production tested. table 4. static electrical characteristics (continued) characteristics noted under conditions 6.0 v d v pwr d 20 v, 3.0 v d v dd d 5.5 v, - 40 q c d t a d 125 q c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 9 35xs3400 electrical characteristics static electrical characteristics outputs hs0 to hs3 (continued) c sr0 current recopy temperature drift (6.0 v < v hs[0:3] < 20 v) (18) output current 2.0 a ' (c sr0_0 )/ ' (t) 0.04 %/ q c current sense ratio (c sr1 ) accuracy (6.0 v < v hs[0:3] < 20 v) output current 6.25 a 39.5 a c sr1_0_acc -17 -12 ? ? +17 +12 % current sense clamp voltage csns open; i hs[0:3] = 2.0 a with c sr0 ratio v cl(csns) v dd +0.25 ? v dd +1.0 v off open-load detection source current (19) i old(off) 30 ? 100 p a off open-load fault detection voltage threshold v old(thres) 2.0 3.0 4.0 v on open-load fault detection current threshold i old(on) 100 300 600 ma on open-load fault detection current threshold with led v hs[0:3] = v pwr - 0.75 v i old(on_led) 2.5 5.0 10 ma output short to v pwr detection voltage threshold output programmed off v osd(thres) v pwr -1.2 v pwr -0.8 v pwr -0.4 v output negative clamp voltage 0.5 a < i hs[0:3] < 5.0 a, output programmed off v cl - 22 ? -16 v output over-temperature shutdown for 4.5 v < vpwr < 28 v t sd 155 175 195 q c notes 18. based on statistical data: delta(c sr0 )/delta(t)={(measured i csns at t 1 - measured i csns at t 2 ) / measured i csns at room} / {t 1 -t 2 }. no production tested. 19. output off open-load detection current is the current requir ed to flow through the load for the purpose of detecting the exi stence of an open-load condition when the specific output is commanded off. pull-up current is measured for v hs =v old(thres) table 4. static electrical characteristics (continued) characteristics noted under conditions 6.0 v d v pwr d 20 v, 3.0 v d v dd d 5.5 v, - 40 q c d t a d 125 q c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 10 freescale semiconductor 35xs3400 electrical characteristics static electrical characteristics control interface input logic high voltage (20) v ih 2.0 ? v dd +0.3 v input logic low voltage (20) v il -0.3 ? 0.8 v input logic pull-down current (sclk, si) (23) i dwn 5.0 ? 20 p a input logic pull-up current ( cs ) (24) i up 5.0 ? 20 p a so, fs tri-state capacitance (21) c so ? ? 20 pf input logic pull-down resistor ( rst , wake and in[0:3]) r dwn 125 250 500 k : input capacitance (21) c in ? 4.0 12 pf wake input clamp voltage (22) , i cl(wake) < 2.5 ma 35xs3400c 35xs3400d v cl(wake) 18 20 25 27 32 35 v wake input forward voltage i cl(wake) = -2.5 ma v f(wake) - 2.0 ? - 0.3 v so high state output voltage i oh = 1.0 ma v soh v dd -0.4 ? ? v so and fs low-state output voltage i ol = -1.0 ma v sol ? ? 0.4 v so, csns and fs tri-state leakage current cs = v ih and 0 v < v so < v dd , or fs = 5.5 v, or csns=0.0 v i so(leak) - 2.0 0 2.0 p a fsi external pull-down resistance (25) watchdog disabled watchdog enabled rfs ? 10 0 infinite 1.0 ? k : notes 20. upper and lower logic threshold voltage range applies to si, cs , sclk, rst , in[0:3] and wake input signals. the wake and rst signals may be supplied by a derived voltage referenced to v pwr . 21. input capacitance of si, cs , sclk, rst , in[0:3] and wake. this parameter is guaranteed by process monitoring but is not production tested. 22. the current must be limited by a series resistance when using voltages > 7.0 v. 23. pull-down current is with v si > 1.0 v and v sclk > 1.0 v. 24. pull-up current is with v cs < 2.0 v. cs has an active internal pull-up to v dd . 25. in fail-safe hs[0:3] depends respectively on on [0:3]. fsi has an active internal pull-up to v reg ~ 3.0 v. table 4. static electrical characteristics (continued) characteristics noted under conditions 6.0 v d v pwr d 20 v, 3.0 v d v dd d 5.5 v, - 40 q c d t a d 125 q c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 11 35xs3400 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 5. dynamic electri cal characteristics characteristics noted under conditions 6.0 v d v pwr d 20 v, 3.0 v d v dd d 5.5 v, - 40 q c d t a d 125 q c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit power output timing hs0 to hs3 output rising medium slew rate (medium speed slew rate / sr[1:0]=00) (26) v pwr = 14 v sr r_00 0.2 0.4 0.8 v/ p s output rising slow slew rate (low speed slew rate / sr[1:0]=01) (26) v pwr = 14 v sr r_01 0.1 0.2 0.4 v/ p s output falling fast slew rate (high speed slew rate / sr[1:0]=10) (26) v pwr = 14 v sr r_10 0.4 0.8 1.6 v/ p s output falling medium slew rate (medium speed slew rate / sr[1:0]=00) (26) v pwr = 14 v sr f_00 0.2 0.4 0.8 v/ p s output falling slow slew rate (low speed slew rate / sr[1:0]=01) (26) v pwr = 14 v sr f_01 0.1 0.2 0.4 v/ p s output rising fast slew rate (high speed slew rate / sr[1:0]=10) (26) v pwr = 14 v sr f_10 0.4 0.8 1.6 v/ p s output turn-on delay time (27) v pwr = 14 v for medium speed slew rate (sr[1:0]=00) t dly(on) 35 60 85 p s output turn-off delay time (28) v pwr = 14 v for medium speed slew rate (sr[1:0]=00) t dly(off) 35 60 85 p s driver output matching slew rate (sr r /sr f ) v pwr = 14 v @ 25c and for medium speed slew rate (sr[1:0]=00) ' sr 0.8 1.0 1.2 driver output matching time ( t dly(on) - t dly(off) ) v pwr = 14 v, f pwm = 240hz, pwm duty cycle = 50%, @ 25c for medium speed slew rate (sr[1:0]=00) ' t rf -25 0 25 p s notes 26. rise and fall slew rates measured across a 5.0 : resistive load at high side output = 30% to 70% (see figure 4 , page 16 ). 27. turn-on delay time measured fr om rising edge of any signal (in[0 : 3] and cs ) that would turn the output on to v hs[0 : 3] = v pwr / 2 with r l = 5.0 : resistive load. 28. turn-off delay time measured fr om falling edge of any signal (in[0 : 3] and cs ) that would turn the output off to v hs[0 : 3] =v pwr / 2 with r l = 5.0 : resistive load.
analog integrated circuit device data 12 freescale semiconductor 35xs3400 electrical characteristics dynamic electrical characteristics power output timing hs0 to hs3 (continued) fault detection blanking time (29) 35xs3400c 35xs3400d t fault - - 5.0 5.0 20 10 p s output shutdown delay time (30) 35xs3400c 35xs3400d t detect - - 7.0 7.0 30 20 p s cs to csns valid time (31) t cnsval ? 70 100 p s watchdog time-out (32) t wdto 217 310 400 ms on open-load fault cyclic detection time with led - f in0 / 128 - ms notes 29. time necessary to report the fault to fs pin. 30. time necessary to switch-off the output in case of ot or oc or sc or uv fault detection (from negative edge of fs pin to hs voltage = 50% of v pwr 31. time necessary for the csns to be with 5% of the targeted value. 32. for fsi open, the watchdog timeout delay measured from the ri sing edge of rst, to hs[0,2] output state depend on the corresp onding input command. table 5. dynamic electrical characteristics (continued) characteristics noted under conditions 6.0 v d v pwr d 20 v, 3.0 v d v dd d 5.5 v, - 40 q c d t a d 125 q c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 13 35xs3400 electrical characteristics dynamic electrical characteristics output over-current time step oc[1:0]=00 (slow by default) oc[1:0]=01 (fast) oc[1:0]=10 (medium) oc[1:0]=11 (very slow) t oc1_00 t oc2_00 t oc3_00 t oc4_00 t oc5_00 t oc6_00 t oc7_00 t oc1_01 t oc2_01 t oc3_01 t oc4_01 t oc5_01 t oc6_01 t oc7_01 t oc1_10 t oc2_10 t oc3_10 t oc4_10 t oc5_10 t oc6_10 t oc7_10 t oc1_11 t oc2_11 t oc3_11 t oc4_11 t oc5_11 t oc6_11 t oc7_11 3.4 1.0 1.4 2.0 3.4 8.4 31.2 1.72 0.56 0.72 1.02 1.56 4.28 15.4 6.8 2.2 2.8 4.0 6.8 17 6.24 13.7 4.5 5.9 8.1 13.7 34.2 124.9 5.0 1.72 2.0 3.0 5.0 12.2 44.6 2.48 0.8 1.04 1.58 2.24 6.12 22.2 9.8 3.2 4.2 5.8 9.8 24.4 89.2 19.6 6.4 8.4 11.6 19.6 48.8 178.4 6.6 2.0 2.6 4.0 6.74 16 48 3.22 1.04 1.36 1.92 2.92 7.96 29 12.8 4.2 5.6 7.6 12.8 31.8 116 25.5 8.3 10.9 15.1 25.5 63.4 231.9 ms table 5. dynamic electrical characteristics (continued) characteristics noted under conditions 6.0 v d v pwr d 20 v, 3.0 v d v dd d 5.5 v, - 40 q c d t a d 125 q c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 14 freescale semiconductor 35xs3400 electrical characteristics dynamic electrical characteristics bulb cooling time step cb[1:0]=00 or 11 (medium) cb[1:0]=01 (fast) cb[1:0]=10 (slow) t bc1_00 t b c2_00 t b c3_00 t b c4_00 t b c5_00 t b c6_00 t b c1_01 t b c2_01 t b c3_01 t b c4_01 t b c5_01 t bc6_01 t b c1_10 t b c2_10 t b c3_10 t b c4_10 t b c5_10 t b c6_10 582 312 356 416 502 628 296 156 176 202 256 452 1166 624 714 834 1002 1256 834 448 510 596 718 898 418 224 254 290 360 648 1668 894 1022 1192 1434 1796 1084 584 664 776 934 1168 544 292 332 378 468 884 2170 1164 1310 1552 1866 2340 ms pwm module timing input pwm clock range on in0 f in0 7.68 ? 30.72 khz input pwm clock low frequency detection range on in0 (33) f in0(low) 1.0 2.0 4.0 khz input pwm clock high frequency detection range on in0 (33) f in0(high) 100 200 400 khz output pwm frequency range f pwm ? ? 1.0 khz output pwm frequency accuracy using calibrated oscillator a fpwm(cal) -10 ? +10 % default output pwm frequency using internal oscillator f pwm(0) 84 120 156 hz cs calibration low minimum time detection range t csb(min) 14 20 26 p s cs calibration low maximum tine detection range t csb(max) 140 200 260 p s output pwm duty-cycle range for f pwm = 400 hz (34) r pwm _400 10 ? 98 % output pwm duty-cycle range for f pwm = 200 hz (34) r pwm _200 5.0 ? 98 % output pwm duty-cycle range for f pwm = 1.0 khz for high speed slew rate (34) r pwm _1k 6.0 ? 94 % input timing direct input toggle timeout t in 175 250 325 ms autoretry timing autoretry period t auto 105 150 195 ms notes 33. clock fail detector available fo r pwm_en bit is set to logic [1] and clock_sel is set to logic [0]. 34. the pwm ratio is measured at v hs = 50% of v pwr and for the default sr value. it is possible to put the device fully-on (pwm duty-cycle 100%) and fully-off (duty-cycle 0%). for values outside this r ange, a calibration is needed between the pwm duty-cycle programm ing and the pwm on the output with r l = 5.0 : resistive load. table 5. dynamic electrical characteristics (continued) characteristics noted under conditions 6.0 v d v pwr d 20 v, 3.0 v d v dd d 5.5 v, - 40 q c d t a d 125 q c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 15 35xs3400 electrical characteristics dynamic electrical characteristics temperature on the gnd flag thermal prewarning detection (35) t otwar 110 125 140 c analog temperature feedback at t a = 25c with r csns =2.5 k : t feed 1.15 1.20 1.25 v analog temperature feedback derating with r csns =2.5 k : (36) dt feed -3.5 -3.7 -3.9 mv/c spi interface characteristics (35) maximum frequency of spi operation f spi ? ? 8.0 mhz required low state duration for rst (37) t w rst 10 ? ? p s rising edge of cs to falling edge of cs (required setup time) (38) t cs ? ? 1.0 p s rising edge of rst to falling edge of cs (required setup time) (38) t enbl ? ? 5.0 p s falling edge of cs to rising edge of sclk (required setup time) (38) t lead ? ? 500 ns required high state duration of sclk (required setup time) (38) t wsclkh ? ? 50 ns required low state duration of sclk (required setup time) (38) t wsclkl ? ? 50 ns falling edge of sclk to rising edge of cs (required setup time) (38) t lag ? ? 60 ns si to falling edge of sclk (required setup time) (39) t si (su) ? ? 37 ns falling edge of sclk to si (required setup time) (39) t si (hold) ? ? 49 ns so rise time c l = 80 pf t rso ? ? 13 ns so fall time c l = 80 pf t fso ? ? 13 ns si, cs , sclk, incoming signal rise time (39) t rsi ? ? 13 ns si, cs , sclk, incoming signal fall time (39) t fsi ? ? 13 ns time from rising edge of sclk to so low logic level (40) t so(en) ? ? 60 ns time from rising edge of sclk to so high logic level (41) t so(dis) ? ? 60 ns notes 35. parameters guaranteed by design. 36. value guaranteed per statistical analysis 37. rst low duration measured with outputs enabl ed and going to off or disabled condition. 38. maximum setup time required for the 35xs3400 is the minimum guaranteed time needed from the microcontroller. 39. rise and fall time of incoming si, cs , and sclk signals suggested for design consideration to prevent the occurrence of double pulsing. 40. time required for output status data to be available for use at so. 1.0 k : on pull-up on cs . 41. time required for output status data to be terminated at so. 1.0 k : on pull-up on cs . table 5. dynamic electrical characteristics (continued) characteristics noted under conditions 6.0 v d v pwr d 20 v, 3.0 v d v dd d 5.5 v, - 40 q c d t a d 125 q c, gnd = 0 v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 16 freescale semiconductor 35xs3400 electrical characteristics timing diagrams timing diagrams v pwr v hs[0:3] t dly(on) t dly(off) low logic level 70% v pwr 30% v pwr sr f sr r 50%v pwr r pwm cs high logic level v hs[0:3] time time time low logic level in[0:3] high logic level time or figure 4. output slew rate and time delays i och 1 t oc5 t oc4 t oc2 t oc1 time load current i och2 i oc1 i oc3 i oc4 i oclo4 i oclo3 i oc2 t oc3 t oc6 t oc7 i oclo2 i oclo1 figure 5. over-current shutdown protection
i och 1 t b c5 t b c4 t b c2 t b c1 previous off duration (toff) i och2 i oc1 i oc3 i oc4 i oclo4 i oclo3 i oc2 t b c3 t b c6 i oclo2 i oclo1 analog integrated circuit device data freescale semiconductor 17 35xs3400 electrical characteristics timing diagrams figure 6. bulb cooling management si rstb csb sclk don?t care don?t care don?t care valid valid vih vil vih vih vih vil vil vil twrstb tlead twsclkh trsi tlag tsisu twsclkl tsi(hold) tfsi 0.7 vdd 0.2 vdd 0.7vdd 0.2vdd 0.2vdd 0.7vdd 0.7vdd tcsb tenbl rst sclk si cs 10% v dd t w rst t enbl 10% v dd t lead t wsclkh t rsi 90% v dd 10% v dd 90% v dd 10% v dd t si(su) t wsclkl t si(hold) t fsi 90% v dd t cs t lag v ih v ih v il v il v ih v il v ih v ih figure 7. input timing switching characteristics
so so sclk voh vol voh vol voh vol tfsi tdlylh tdlyhl t valid trso tfso 3.5v 50% trsi high-to-low 1.0v 0.7 vdd 0.2vdd 0.2 vdd 0.7 vdd low-to-high t rsi t fsi 90% v dd sclk so so v oh v ol v oh v ol v oh v ol 10% v dd 10% v dd 90% v dd t rso t fso 10% v dd t so(en) t so(dis) low to high high to low t valid 90% v dd analog integrated circuit device data 18 freescale semiconductor 35xs3400 electrical characteristics timing diagrams figure 8. sclk waveform and valid so data delay time
analog integrated circuit device data freescale semiconductor 19 35xs3400 functional description introduction functional description introduction the 35xs3400 is one in a family of devices designed for low-voltage automotive lighting applications. its four low r ds(on) mosfets (quad 35 m : ) can control four separate 28 w bulbs. programming, control and diagnostics are accomplished using a 16-bit spi interface. it s output with selectable slew- rate improves electromagnetic compatibility (emc) behavior. additionally, each output has it s own parallel input or spi control for pulse-width modulati on (pwm) control if desired. the 35xs3400 allows the user to program via the spi the fault current trip levels and duration of acceptable lamp inrush. the device has fail-safe mode to provide fail-safe functionality of the outputs in case of mcu damaged. functional pin description output current monitoring (csns) the current sense pin provides a current proportional to the designated hs0 : hs3 output or a voltage proportional to the temperature on the gnd flag. that current is fed into a ground-referenced resistor (4.7 k : typical) and its voltage is monitored by an mcu's a/d. the output type is selected via the spi. this pin can be tri-stated through the spi. direct inputs (in0, in1, in2, in3) each in input wakes the device. the in0 : in3 high side input pins are also used to directly control hs0 : hs3 high side output pins. if the outputs are controlled by the pwm module, the external pwm clock is applied to in0 pin. these pins are to be driven with cmos levels, and they have a passive internal pull-down, r dwn . fault status ( fs ) this pin is an open drain configured output requiring an external pull-up resistor to v dd for fault reporting. if a device fault condition is detected, this pin is active low. specific device diagnostics and faults are reported via the spi so pin. wake the wake input wakes the de vice. an internal clamp protects this pin from high da maging voltages with a series resistor (10k : typ). this input has a passive internal pull- down, r dwn . reset ( rst ) the reset input wakes the device. this is used to initialize the device configuration and fault registers, as well as place the device in a low-current sleep mode. the pin also starts the watchdog timer when transitioning from logic [0] to logic [1]. this pin has a passive internal pull-down, r dwn . chip select ( cs ) the cs pin enables communication with the master microcontroller (mcu). when this pin is in a logic [0] state, the device is capable of transferring information to, and receiving information from, the mcu. the 35xs3400 latches in data from the input shift registers to the addressed registers on the rising edge of cs . the device transfers status information from the power outpu t to the shift register on the falling edge of cs . the so output driver is enabled when cs is logic [0]. cs should transition from a logic [1] to a logic [0] state only when sclk is a logic [0]. cs has an active internal pull-up from v dd , i up . serial clock (sclk) the sclk pin clocks the internal shift registers of the 35xs3400 device. the serial input (si) pin accepts data into the input shift register on the falling edge of the sclk signal while the serial output (so) pin shifts data information out of the so line driver on the rising edge of the sclk signal. it is important the sclk pin be in a logic low state whenever cs makes any transition. for this reason, it is recommended the sclk pin be in a logic [0] whenever the device is not accessed ( cs logic [1] state). sclk has an active internal pull-down. when cs is logic [1], signals at the sclk and si pins are ignored and so is tri-stated (high-impedance) (see figure 9 , page 22 ). sclk input has an active internal pull- down, i dwn . serial input (si) this is a serial interface (si) command data input pin. each si bit is read on the falling edge of sclk. a 16-bit stream of serial data is required on the si pin, starting with d15 (msb) to d0 (lsb). the internal registers of the 35xs3400 are configured and controlled using a 5-bit addressing scheme described in table 10 , page 30 . register addressing and configuration are described in table 11 , page 30 . si input has an active internal pull-down, i dwn . digital drain voltage (vdd) this pin is an external voltage input pin used to supply power to the spi circuit. in the event v dd is lost (v dd failure), the device goes to fail-safe mode.
analog integrated circuit device data 20 freescale semiconductor 35xs3400 functional description functional internal block description ground (gnd) these pins are the ground for the device. positive power supply (vpwr) this pin connects to the positive power supply and is the source of operational power for the device. the vpwr contact is the backside surface mount tab of the package. serial output (so) the so data pin is a tri-stateable output from the shift register. the so pin remains in a high-impedance state until the cs pin is put into a logic [0] state. the so data is capable of repo rting the status of the ou tput, the device configuration, the state of the key inputs, et c. the so pin changes state on the rising edge of sclk and reads out on the falling edge of sclk. so reporting descriptions are provided in table 23 , page 35 . high side outputs (hs3, hs1, hs0, hs2) protected 35 m high side power outputs to the load. fail-safe input (fsi) this pin incorporates an active internal pull-up current source from internal supply (v reg ). this enables the watchdog timeout feature. when the fsi pin is opened, the watchdog circuit is en abled. after a watchdog timeout occurs, the output states depends on in[0:3]. when the fsi pin is connect e d to gnd, the watchdog circuit is disabled. the output states depends on in[0:3] in case of v dd failure condition, in case v dd failure detection is activated (vdd_fail_en bit sets to logic [1]). functional internal block description power supply mcu interface and output control spi interface parallel control inputs pwm controller self- protected high side switches hs0-hs3 mcu interface power supply the 35xs3400 is designed to operate from 4.0 v to 28 v on the vpwr pin. characteristics are provided from 6.0 v to 20 v for the device. the vpwr pin supplies power to internal regulator, analog, an d logic circuit blocks. the vdd supply is used for serial peripheral interface (spi) communication in order to configure and diagnose the device. this ic architecture provides a low quiescent current sleep mode. applying v pwr and v dd to the device will place the device in the normal mode. the device will transit to fail-safe mode in case of failures on the spi or/and on vdd voltage. high side switches: hs0 ? hs3 these pins are the high side outputs controlling automotive lamps located for the rear of vehicle, such as 28 w bulbs and led modules. 55 w/65 w lamps can be drive n for two outputs short ed together. those n-channel mosfets with 35 m r ds(on) are self-protected and present extended diagnostics in order to detect bulb outage and short-circuit fault condition. the hs output is actively clamped during turn off of inductive loads and inductive battery line. when driving dc motor or solenoid loads demanding multipl e switching, an external recirculation device must be used to maintain the device in its safe operating area. mcu interface and output control in normal mode, each bulb is controlled directly from the mcu through spi. a pulse widt h modulation control module allows improvement of lamp lifetime with bulb power
analog integrated circuit device data freescale semiconductor 21 35xs3400 functional description functional internal block description regulation (pwm frequency range from 100 to 400 hz) and addressing the dimming application (day running light). an analog feedback output provides a current proportional to the load current or the temperature of the board. the spi is used to configure and to read the di agnostic status (faults) of high side outputs. the re ported fault conditi ons are: open load, short-circuit to battery, short- circuit to ground (over-current and severe short-circuit), thermal shutdown, and under/over- voltage. thanks to accurate and configurable over-current detection circuitry and wire-har ness optimization, the vehicle is lighter. in fail-safe mode, each lamp is controlled with dedicated parallel input pins. the device is configured in default mode.
analog integrated circuit device data 22 freescale semiconductor 35xs3400 functional device operation functional internal block description functional device operation spi protocol description the spi interface has a full duplex, three-wire synchronous data transfer with four i/o lines associated with it: serial input (si), serial ou tput (so), serial clock (sclk), and chip select ( cs ). the si / so pins of the 35xs3400 follow a first-in first-out (d15 to d0) protocol , with bot h input and output words transferring the most significant bit (msb) first. all inputs are compatible with 5.0 v or 3.3 v cmos logic levels. cs csb si sclk so d15 d1 d2 d3 d4 d5 d6 d7 d8 d9 d14 d13 d12 d11 d10 od12 d0 od13 od14 od15 od6 od7 od8 od9 od10 od11 od1 od2 od3 od4 od5 1. rstb is in a logic h state during the above operation. 2. do, d1, d2, ... , and d15 relate to the most recent ordered entry of program data into the lux ic notes: od0 cs device. 1. rst is a logic [1] state during the above operation. 2. d15 : d0 relate to the most recent ordered entry of data into the device. 3. od15 : od0 relate to the first 16 bits of ordered fault and status data out of the device. notes figure 9. single 16-bit word spi communication
analog integrated circuit device data freescale semiconductor 23 35xs3400 functional device operation operational modes operational modes the 35xs3400 has four operating modes: sleep, normal, fail-safe and fault. table 6 and figure 11 summarize details contained in succeeding paragraphs. the figure 10 describes an internal signal called in_on[x] depending on in[x] input. in_on[x] in[x] t in figure 10. in_on[x] internal signal the 35xs3400 transits to operating modes according to th e following signals: ? wake-up = rst or wake or in_on[0] or in_on[1] or in_on[2] or in_on[3], ? fail = (v dd failure and vdd_fail_en) or ( watchdog time-out and fsi input not shorted to ground ), ? fault = oc[0:3] or ot[0 :3] or sc[0:3] or uv ( uv ) or ( ov and ov_dis ). table 6. 35xs3400 operating modes mode wake-up fail fault comments sleep 0 x x device is in sleep mode. all outputs are off. normal 1 0 0 device is currently in normal mode. watchdog is active if enabled. fail-safe 1 1 0 device is currently in fail-safe mode due to watchdog timeout or v dd failure conditions. the output states depend on the corresponding input in case fsi is open. fault 1 x 1 device is currently in fault mode. the faulted output(s) is (are) off. the safe autoretry circuitry is active to turn-on again the output(s). x = don?t care. sleep (fail=0) and (wake-up=1) and (fault=0) (wake-up=0) fail-safe normal (wake-up=0) (fail=1) and (wake-up=1) and (fault=0) (fail=0) and (wake-up=1) and (fault=0) (wake-up=1) and (fail=1) and (fault=0) fault (wake-up=0) (wake-up=1) and (fault=1) (fail=0) and (wake-up=1) and (fault=1) (fail=1) and (wake-up=1) and (fault=1) (fail=0) and (wake-up=1) and (fault=0) (fail=1) and (wake-up=1) and (fault=0) figure 11. operating modes sleep mode the 35xs3400 is in sleep mode when: ?v pwr and v dd are within the normal voltage range, ? wake-up = 0, ? fail = x, ?fault = x. this is the default mode of the device after first applying ba ttery voltage (vpwr) prior to any i/o transitions. this is also the state of the de vice when the wake and rst and in_on[0:3] are logic [0]. in the sleep mo de, the output and all unused internal circuitry, such as the internal regulator, are off to minimize draw current. in addition, all spi-configurable features of the device are as if set to logic [0].
analog integrated circuit device data 24 freescale semiconductor 35xs3400 functional device operation operational modes normal mode the 35xs3400 is in normal mode when: ?v pwr and v dd are within the normal voltage range, ? wake-up = 1, ? fail = 0, ?fault = 0. in this mode, the nm bit is set to lfault_contrologic [1] and th e outputs hs[0:3] are under c ontrol, as defined by hson signal: hson[x] = ( ( (in[x] and dir_dis [x]) or on bit[x] ) and pwm_en ) or (on bit [x] and duty_cycle[x] and pwm_en). in this mode and also in fail-safe, the fault condition reset dep ends on fault_control signal, as defined below: fault_control[x] = ( (in_on[x] and dir_dis [x]) and pwm_en ) or (on bit [x]). programmable pwm module the outputs hs[0:3] are cont roll ed by the programmable pwm module if pwm_en and on bits are set to logic [1]. the clock frequency from in0 input pin or from internal clock is the factor 2 7 (128) of the output pwm frequency (clock_sel bit). the outputs hs[0:3] can be controlled in the range of 5% to 98% with a reso lution of 7 bits of duty cycle ( table 7 ). the state of other in pin is ignored. table 7. output pwm resolution on bit duty cycle output state 0 x off 1 0000000 pwm (1/128 duty cycle) 1 0000001 pwm (2/128 duty cycle) 1 0000010 pwm (3/128 duty cycle) 1 n pwm ((n+1)/128 duty cycle) 1 1111111 fully on table 8. output pwm switching delay delay bits output delay 000 no delay 001 16 pwm clock periods 010 32 pwm clock periods 011 48 pwm clock periods 100 64 pwm clock periods 101 80 pwm clock periods 110 96 pwm clock periods 111 112 pwm clock periods the timing includes seven programmable pwm switching delay (number of pwm clock rising edges) to improve overall emc behavior of the light module ( table 8 ). the clock frequency from in0 is permanently monitored in order to report a clock failure in case of the frequency is out a specified frequency range (from f in0(low) to f in0(high) ). in case of clock failure, no pwm feature is provided, the on bit defines the outputs state and the clock_fail bit reports [1]. calibratable internal clock the internal clock can vary as much as +/-30 percent correspo nding to typical f pwm(0) output switching period. using the existing spi inputs and the precision timing referen ce already available to the mcu, the 35xs3400 allows clock period setting within 10 percent of accuracy. calibrating the internal clock is initiated by defined word to calr register. the calibration pu lse is provided by the mcu. the pulse is sent on the cs pin after the spi word is launched. at the moment, the cs pin transitions from logic [1] to [0] until from logic [0] to [1] determine the period of internal clock with a multiplicative factor of 128. cs si calr si command ignored internal clock duration in case of negative cs pulse is outside a predefined time range (from t csb(min) to t csb(max) ), the calibration event will be ignored and the internal clock will be unaltered or reset to default value (f pwm(0) ) if this was not calibrated before. the calibratable clock is used, instead of the clock from i n0 input, when clock_sel is set to [1].
analog integrated circuit device data freescale semiconductor 25 35xs3400 functional device operation operational modes fail-safe mode the 35xs3400 is in fail-safe mode when: ?v pwr is within the normal voltage range, ? wake-up = 1, ? fail = 1, ?fault = 0. watchdog if the fsi input is not gr ound ed, the watchdog timeout detection is active when eit her the wake or in_on[0:3] or rst input pin transitions from logic [0] to logic [1]. the wake inp ut is capable of being pulled up to vpwr with a series of limiting resistance limiting the internal clamp current according to the specification. the watchdog timeout is a multiple of an internal oscillator . as long as the wd bit (d15) of an incoming spi message is toggled within the minimum watchdog timeout period (wdto), the device will operate normally. fail-safe conditions if an internal watchdog time-out occurs before the wd bit fo r fsi open ( table 9 ) or in case of v dd failure condition (v dd < v dd(fail) )) for vdd_fail_en bit is set to logic [1], the device will revert to a fail-safe mode until the wd bit is written to logic [1] (see fail-safe to normal mode transition paragraph) and v dd is within the norm al voltage range. table 9. spi watchdog activation typical rfsi ( ) watchdog 0 (shorted to ground) disabled (open) enable during the fail-safe mode, the outputs will depend on the corresponding input. the spi register content is reset to their default value (except por bit) and fault protections are fully operational. the fail-safe mode can be det ected b y monitoring the nm bit is set to [0]. normal & fail-saf e mode transitions transition fail-safe to normal mode to leave the fail-safe mode, v dd must be in nominal voltage and the microcontroller has to send a spi command with wdin bit set to logic [1]; the other bits are not considered. the previous latc hed faults are reset by the transition into normal mode (autoretry included). moreover, the device can be brought out of the fail-safe mode due to watchdog timeout issue by forcing the fsi pin to logic [0]. transition normal to fail-safe mode to leave the normal mode, a fail-safe condition must occurred (fail=1). the previous la tched faults are reset by the transition into fail-safe mode (autoretry included). fault mode the 35xs3400 is in fault mode when: ?v pwr and v dd are within the normal voltage range, ? wake-up = 1, ? fail = x, ? fault=1. this device indicates the faults below as they occur by drivi ng the fs pin to logic [0] for rst input is pulled up: ?over-temperature fault, ?over-current fault, ?severe short-circuit fault, ?output(s) shorted to vpwr fault in off state, ?open load fault in off state, ?over-voltage fault (enabled by default), ?under-voltage fault. the fs pin will automatically return to logic [1] when the fault condi tion is removed, except for over-current, severe short-circuit, over-temperature and under-voltage which will be reset by a new turn-on command (each fault_control signal to be toggled). fault information is retained in the spi fault register and is available (and reset) via the so pin during the first valid spi communication. the open load fault in on state is only reported through spi reg ister without effect on the corresponding output state (hs[x]) and the fs pin. start-up sequence the 35xs3400 enters in normal mode after start-up if following sequence is provided: ?vpwr and vdd power supplies must be above their under-voltage thresholds, ?generate wake-up event (wake-up=1) from 0 to 1 on rstb. the device switches to normal mode with spi register content is reset (as defined in table 11 and table 23 ). all features of 35xs3400 will be available after 50 s typical and all spi registers are set to default values (set to logic [0]). the uv fault is reported in the spi status registers. and, in case of the pwm module is used (pwm_en bit is set to logic [1]) with an external reference clock: ?apply pwm clock on in0 input pin after maximum 200 s (min. 50 s). if the correct start-up sequence is not provided, the pwm function is not guaranteed.
analog integrated circuit device data 26 freescale semiconductor 35xs3400 functional device operation protection and di agnostic features protection and diagnostic features protections over-temperature fault the 35xs3400 incorporates over-te mperature detection and shutdown circuitry fo r each output structure. two cases need to be considered when the output te mperature is higher than t sd : ?if the output command is on: the corresponding output is l atched off. fs will be also latched to logic [0]. to delatch the fault and be able to turn on again the outputs, the failure condition must disappear and the autoretry circuitry must be active or the corresponding output must be commanded off and then on (toggling fault_control signal of corresponding output) or v supply(por) condition if v dd = 0. ?if the output command is off: fs will go to logic [0] until the corresponding output temperature will be below t sd . for both cases, the fault register o t[0:3] bit into the status register will be set to [1]. the fault bits will be cleared in the status register after a spi read command. over-current fault the 35xs3400 incorporates out put shutdown in order to protect each output structure ag ainst resistive short-circuit condition. this protection is composed by eight predefined current levels (time dependent) to fit 28 w bulb profiles. in the first turn-on, the lamp filament is cold and the current will be huge. fault_control signal transition from logic [0] to [1] or an autoretry define this event. in this case, the over-current protection will be fitted to inrush current, as shown in figure 5 . this over-current protection is programmable: oc[1:0] bits select over-current slope speed and ochi1 current step can be removed in ca se the ochi bit is set to [1]. hson signal over-current thresholds pwm fault_control hson in steady state, the wire ha rness will be protected by oclo2 current level by default. three other dc over-current levels are available: oclo1 or oclo3 or oclo4 based on the state of the oclo[1,0] bits. if the load current level ever reaches the over-current de tection level, the correspondi ng output will latch the output off and fs will be also latched to logic [0]. to delatch the fault and be able to turn on again the corresponding output, the failure condition must disappear and the autoretry circuitry must be active or the corresponding output must be commanded off and then on (toggling fault_control signal of corresponding output) or v supply(por) condition if v dd = 0. the spi fault report (oc[0:3] bits) is removed after a read op eration. in normal mode using the internal pwm module, the 35 xs3400 also incorporates a cooling bulb filament management, if the oc_mode is set to logic [1]. in this case, the 1 st step of multi-step over-current protection will depend to the previous off duration, as illustrated in figure 6 . the following figure illustrates the current level will be used in function to the duration of prev ious off state (toff). the slope of cooling bulb emulator is co nfigurable with ocoffcb[1:0] bits. over-current thresholds toff depending to toff cooling pwm hson signal fault_control hson depending on toff severe short-circuit fault the 35xs3400 provides output shutdow n in order to protect each output in case of severe short-circuit during of the output switching. if the short-circuit impedance is below r short , the device will latch the output off, fs will go to logic [0] and the fault register sc[0:3] bit will be set to [1]. to delatch the fault and be able to turn on again the outputs, the failure condition must disappear and the corresponding output must be commanded off, and then on (toggling fault_control signal of corresponding output) or v supply(por) condition, if v dd = 0. the spi fault report (sc[0:3] bits) is removed after a read op eration.
analog integrated circuit device data freescale semiconductor 27 35xs3400 functional device operation protection and di agnostic features over-voltage fault (enabled by default) by default, the over-voltage protection is enabled. the 35xs3400 shuts down all outputs and fs will go to logic [0] during an over-voltage fault condition on the vpwr pin (v pwr > v pwr(ov) ). the outputs remain in the off state until the over-voltage condition is removed (v pwr < v pwr(ov) - v pwr(ovhys) ). when experiencing this fault, the ovf fault bit is set to logic [1] and cleared after either a valid spi read. the over-voltage protection can be disabled through spi (ov_dis bit is disabled set to logic [1]). the fault register reflects any over-voltage condition (v pwr > v pwr(ov) ). this over-voltage diagnosis, as a warning, is removed after a read operation, if the fault condition disappears. the hs[0:3] outputs are not commanded in r ds(on) above the ov threshold. in fail-safe mode, the over-voltage activation depends on the rst logic state; enable for rst = 1 and disable for rst = 0. the device is still pr otected with over-temperature protection in case the over -voltage feature is disabled. under-voltage fault the output(s) will latch off at some battery voltage below vpwr (uv) . as long as the v dd level stays within the normal specified range, the internal l ogic states within the device will remain (configuration and reporting). in the case where battery voltage drops below the under- voltage threshold (v pwr < v pwr(uv) ), the outputs will turn off, fs will go to logic [0], and the fault register uv bit will be set to [1]. two cases need to be considered when the battery level recovers (v pwr > v pwr(uv)_up ): ?if the output command is off, fs will go to logic [1], but the uv bit will remain set to 1 until the next read operation (warning report). ?if the output command is on, fs will remain at logic [0]. to delatch the fault and be able to turn on again the outputs, the failure condition must disappear and the autoretry circuitry must be active or the corresponding output must be commanded off and then on (toggling fault_control signal of corresponding output) or v supply(por) condition if v dd = 0. in extended mode , the output is protected by over- temperature shutdown circuitry. all previous latched faults, occurred when vpwr was within the normal voltage range, are guaranteed if vdd is withi n the operational voltage range or until v supply(por) if vdd = 0. any new ot fault is detected (vdd failure included) and reported through spi above vpwr (uv) . the output state is not changed as long as the vpwr voltage does not drop any lower than 3.5 v typical. all latched faults (over-temperature, over-current, severe short-circuit, over and under-voltage) are reset if: ?v dd < v dd(fail) with v pwr in nominal voltage range, ?v dd and v pwr supplies is below v supply(por) voltage value.
off on latched off autoretry off autoretry on (sc=1) (ov=1) (fault_control=1 and ov=0) (fault_control=0 or ov=1) (fault_control=0) (fault_control=0) (fault_control=0) (sc=1) (retry=1) => count=count+1 (retry=1) (count=16) (after retry period and ov=0) (openloadoff=1 or shortvpwr=1 (openloadoff=1 or shortvpwr=1 (openloadoff=1 or shortvpwr=1 (openloadon=1) (openloadon=1) or ov=1) or ov=1) or ov=1) if hson=1 if hson=0 if hson=1 analog integrated circuit device data 28 freescale semiconductor 35xs3400 functional device operation protection and di agnostic features figure 12. auto-retry state machine auto-retry the auto-retry circuitry is used to reactivate the output(s) automatically in case of over-c urrent or over-temperature or under-voltage failure conditions to provide a high availability of the load. auto-retry feature is available in fault mode. it is activated in case of internal retry signal is set to logic [1]: retry[x] = oc[x] or ot[x] or uv. the feature retries to switch -on the output(s) after one auto-retry period (t auto ) with a limitation in term of number of occurrence (16 for each output). the counter of retry occurrences is reset in case of fail-safe to normal or normal to fail-safe mode transitions. at each auto-retry, the over- current detection will be set to default values in order to sustain the inrush current. the figure 12 describes the auto -retry state machine. diagnostic output shorted to vpwr fault the 35xs3400 incorporates output shorted to vpwr detection circuitry in off state. output shorted to vpwr fault is detected if output voltage is higher than v osd(thres) and reported as a fault condition when the output is disabled (off). the output shorted to vpwr fault is latched into the status register after the internal gate voltage is pulled low enough to turn off the output. the os[0:3] and ol_off[0:3] fault bits are set in the status register and fs pin reports in real time the f ault. if the out put shorted to vpwr fault is removed, the stat us register will be cleared after reading the register. the open output shorted to vpw r protection can be disabled through spi (os_dis[0:3] bit). open-load faults the 35xs3400 incorporates th ree dedicated open-load detection circuitries on the output to detect in off and in on state. open-load detection in off state the off output open-load fault is detected when the ou tput voltage is higher than v old(thres) pulled up with internal current source ( i old(off) ) and reported as a fault condition when the output is dis abled (off). the off output open-load fault is latched into the status register or when the internal gate voltage is pulled low enough to turn off the output. the ol_off[0:3] fault bit is set in the status register. if the open load fault is removed ( fs output pin goes to high), the status register will be cleared after reading the register. the off output open-load protection can be disabled throug h spi (oloff_dis[0:3] bit).
analog integrated circuit device data freescale semiconductor 29 35xs3400 functional device operation protection and di agnostic features open-load detection in on state the on output open-load current thresholds can be chosen by spi to detect a standard bulbs or leds (olled[0:3] bit set to logic [1]). in cases where the load current drops below the defined current threshold, the olon bit will be set to a logic [1], the output will stay on and fs will not be disturbed. open-load detection in on state for led open load for leds only (olled[ 0:3] set to logic [1]) is detected periodically each t olled (fully-on, d[6:0]=7f). to detect olled in fully-on state, the output must be on at least t olled. to delatch the diagnosis, the condition should be removed and spi read operation is needed (ol_on[0:3] bit). the on output open-load protection ca n be disabled through spi (olon_dis[0:3] bit). analog current recopy and temperature feedbacks the csns pin is an analog output reporting a current proportional to the designed ou tput current or a voltage proportional to the temperatur e of the gnd flag (pin #14). the routing is spi programmable (temp_en, csns_en, csns_s[1,0] and csns_ratio_s bits). in case the current recopy is active, the csns output delivers current only during on time of the output switch without overshoot. the maximum current is 2.0 ma typical. the typical value of external cs ns resistor connected to the ground is 4.7 k : . the current recopy is not active in fail-safe mode. temperature prewarning detection in normal mode, the 35xs3400 provides a temperature prewarning reported via spi in case of the temp erature of the gnd flag is higher than t otwar . this diagnosis (otw bit set to [1]) is latched in the spi diagr0 register. to delatch, a read spi command is needed. active clamp on vpwr the device provides an active gate clamp circuit in order to limit the maximum transient vpwr voltage at vpwr (clamp) . in case of overload on an output the corresponding output is turned off which leads to high- voltage at vpwr with an inductive vpwr line. when vpwr voltage exceeds vpwr (clamp) threshold, the turn-off on the corresponding output is deactivated and all hs[0:3] outputs are switched on automatically to demagnetize the inductive battery line. for a long battery line between the battery and the device (> 20 meters), the smart high side switch output may exceed the energy capability in case of a short-circuit. it is recommended to implement a vo ltage transient suppressor to drain the battery line energy. reverse battery on vpwr the output survives the applicat ion of reverse voltage as low as -18 v. under these conditions , the on resistance of the output is 2 times higher t han typical ohmic value in forward mode. no additional passive components are required except on v dd current path. ground disconnect protection in the event the 35xs3400 ground is disconnected from load ground, the device protects itself and safely turns off the output regardless of the state of the ou tput at the time of disconnection (maximum vpwr=16 v). a 10 k : resistor needs to be added between the mcu and each digital input pin in order to ensure that the device turns off in case of ground disconnect and to prevent this pin from exceeding maximum ratings. loss of supply lines loss of vdd if the external v dd supply is disconnected (or not within specification: v dd analog integrated circuit device data 30 freescale semiconductor 35xs3400 functional device operation logic commands and registers emc performances all following tests are performed on freescale evaluation board in accordance with the typical application schematic. the device is protected in case of positive and negative transients on the vpwr line (per iso 7637-2). the 35xs3400 successfully meets the class 5 of the cispr25 emission standard and 200 v/m or bci 200 ma injection level for immunity tests. logic commands and registers serial input communication spi communication is accomplished using 16-bit messages. a message is transm itted by the mcu starting with the msb d15 and ending with the lsb, d0 ( table 10 ). each incoming command message on the si pin can be interpre ted using the following bit assignments: the msb, d15, is the watchdog bit (wdi n). in some cases, output selection is done with bits d14 : d13. the next three bits, d12 : d10, are used to select the command register. the remaining nine bits, d8 : d0, are used to configure and control the outpu ts and their protection features. multiple messages can be transmitted in succession to accommoda te those applications where daisy-chaining is desirable, or to confirm transmitted data, as long as the messages are all multiples of 16 bits. any attempt made to la tch in a message that is not 16 bits will be ignored. the 35xs3400 has defined registers, which are used to config ure the device and to cont rol the state of the outputs. table 11 summarizes the si registers. table 10. si message bit assignment bit sig si msg bit message bit description msb d15 watchdog in: toggled to satisfy watchdog requirements. d14 : d13 register address bits used in some cases for output selection ( table 12 ). d12 : d10 register address bits. d9 not used (set to logic [0]). lsb d8:d0 used to configure the inputs, outputs, and the dev ice protection features and so status content. table 11. serial input address and configuration bit map si register si data d15 d1 4 d1 3 d1 2 d1 1 d1 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 statr_s wdi n x x 0 0 0 0 0 0 0 0 soa4 soa3 soa2 soa1 soa0 pwmr_s wdi n a 1 a 0 0 0 1 0 0 on_s pwm6_s pwm5_s pwm4_s pwm3_s pwm2_s pwm1_s pwm0_s confr0_s wdi n a 1 a 0 0 1 0 0 0 0 0 dir_dis_s sr1_s sr0_s delay2_s delay1_s delay0_s confr1_s wdi n a 1 a 0 0 1 1 0 0 0 retry_ unlimited_s retry_dis_s os_dis_s olon_dis_s oloff_dis_ s olled_en _s csns_ratio _s ocr_s wdi n a 1 a 0 1 0 0 0 0 bc1_s bc0_s oc1_s oc0_s ochi_s oclo1_s oclco0_s oc_mode_ s gcr wdi n 0 0 1 0 1 0 vdd_f ail_en pwm_en clock_sel temp_en csns_en csns1 csns0 x ov_dis calr wdi n 0 0 1 1 1 0 1 0 0 0 1 1 0 1 1 register state after rst =0 or v dd(fail) or v supply(po r) condition 0 0 0 x x x 0 0 0 0 0 0 0 0 0 0
analog integrated circuit device data freescale semiconductor 31 35xs3400 functional device operation logic commands and registers x = don?t care. s = output selection with the bits a 1 a 0 as defined in table 12 . table 11. serial input address and configuration bit map
analog integrated circuit device data 32 freescale semiconductor 35xs3400 functional device operation logic commands and registers device register addressing the following section describes the possible register addresses (d[14:10]) and their impact on device operation. address xx000 ? status register (statr_s) the statr register is used to read the device status and the various configuration register contents without disrupting the device operation or the regist er contents. the register bits d[4:0] determine the content of the first sixteen bits of so data. in addition to the device st atus, this feature provides the ability to read the content of the pwmr_s, confr0_s, confr1_s, ocr_s, gcr and calr registers (refer to the section entitled serial output communication (device status return data) on page 34 . address a 1 a 0 001? output pwm control register (pwmr_s ) the pwmr_s register allows the mcu to control the state of corresponding output throu gh the spi. each output ?s? is independently selected for conf iguration based on the state of the d14 : d13 bits ( table 12 ). table 12. output selection a 1 (d14) a 0 (d13) hs selection 0 0 hs0 (default) 0 1 hs1 1 0 hs2 1 1 hs3 bit d7 sets the output state. a logic [1] enables the correspon ding output switch and a logic [0] turns it off (if in inp ut is also pulled down). bits d6:d0 set the output pwm duty-cycle to one of 128 levels for pwm_en is set to logic [1], as shown table 7 , page 24 . address a 1 a 0 010? output configuration register (confr0_s ) the confr0_s register allows the mcu to configure corresponding output switching through the spi. each output ?s? is independently selected for configuration based on the state of the d14 : d13 bits ( table 12 ). for the selected output, a logic [0] on bit d5 (dir_dis_s) will enable the output for direct control. a logic [1] on bit d5 will disable the output from dire ct control (in this case, the output is only controlled by on bit). d4:d3 bits (sr1_s and sr0_s) are used to select the high or med ium or low speed slew rate for the selected output, the default value [00] corresponds to the medium speed slew rate ( table 13 ). table 13. slew rate speed selection sr1_s (d4) sr0_s (d3) slew rate speed 0 0 medium (default) 0 1 low 1 0 high 1 1 not used incoming message bits d2 : d0 reflect the desired output that w ill be delayed of predefined pwm clock rising edges number, as shown table 8 , page 24 (only available for pwm_en bit is set to logic [1]). address a 1 a 0 011 ? output configuration register (confr1_s) the confr1_s register allo ws the mcu to configure corresponding output fault management through the spi. each output ?s? is independently selected for configuration based on the state of the d14 : d13 bits ( table 12 ). a logic [1] on bit d6 (retry_unlimited_s) disables the au toretry counter for the sele cted output, the default value [0] corresponds to enable auto-retry feature without time limitation. a logic [1] on bit d5 (retry_dis_s) disables the auto- retry fo r the selected output, t he default value [0] corresponds to enable this feature. a logic [1] on bit d4 (os_dis_s) disables the output hard shorted to vpwr protection for the selected output, the default value [0] corresponds to enable this feature. a logic [1] on bit d3 (olon_dis_s) disables the on output op en-load detection for the selected output, the default value [0] corresponds to enable this feature ( table 14 ). a logic [1] on bit d2 (oloff_dis_s) disables the off ou tput open-load detection fo r the selected output, the default value [0] corresponds to enable this feature. a logic [1] on bit d1 (olled_en_s) enables the on output op en-load detection for leds for the selected output, the default value [0] corresponds to on output open-load detection is set for bulbs ( table 14 ). table 14. on open-load selection olon_dis_s (d3) olled_en_s (d1) on openload detection 0 0 enable with bulb threshold (default) 0 1 enable with led threshold 1 x disable a logic [1] on bit d0 (csns_ratio_s) se l ects the high ratio on the csns pin for the corre sponding output. the default value [0] is the low ratio ( table 15 ).
table 15. current sense ratio selection csns_high_s (d0) current sense ratio 0 crs0 (default) 1 crs1 analog integrated circuit device data freescale semiconductor 33 35xs3400 functional device operation logic commands and registers address a 1 a 0 100 ? output over-current register (ocr) the ocr_s register allows the mcu to configure corresponding output over-cu rrent protection through the spi. each output ?s? is independently selected for configuration based on the state of the d14 : d13 bits ( table 12 ). d[7:6] bits allow to mcu to programmable bulb cooling curve and d[5:4] bits inrush curve for selected output, as shown table 16 and table 17 . . table 16. cooling and inrush curve selection bc1_s (d7) bc0_s (d6) profile curves speed 0 0 medium (default) 0 1 slow 1 0 fast 1 1 medium table 17. inrush curve selection oc1_s (d5) oc0_s (d4) profile curves speed 0 0 slow (default) 0 1 fast 1 0 medium 1 1 very slow a logic [1] on bit d3 (ochi_s bit) t he ochi1 level is replaced by ochi2 during t oc1 , as shown figure 13 . i och 1 t oc5 t oc4 t oc2 t oc1 time i och2 i oc1 i oc3 i oc4 t oc3 t oc6 t oc7 i oc2 i oclo4 i oclo3 i oclo2 i oclo1 figure 13. over-current profile with ochi bit set to ?1? the wire harness is protected by one of four possible current levels in steady state, as defined in table 18 . table 18. output steady state selection oclo1 (d2) oclo0 (d1) steady state current 0 0 oclo2 (default) 0 1 oclo3 1 0 oclo4 1 1 oclo1 bit d0 (oc_mode_sel) allows to select the over-current mode, as described table 19 . table 19. over-current mode selection oc_mode_s (d0) over-current mode 0 only inrush current management (default) 1 inrush current and bulb cooling management address 00101 ? global configuration register (gcr) the gcr register allows the mcu to configure the device through the spi. bit d8 allows the mcu to enable or disable the v dd failure detector. a logic [1] on vdd_fail_en bit allows transitioning to fai l-safe mode for v dd < v dd(fail). bit d7 allows the mcu to enable or disable the pwm module. a logic [1] on pwm_en bit allows control of the ou tputs hs[0:3] with pwmr register (the direct input states are ignored). bit d6 (clock_sel) allows to select the clock used as re ference by pwm module, as described in the following table 20 .
table 20. pwm module selection pwm_en (d7) clock_sel (d6) pwm module 0 x pwm module disabled (default) 1 0 pwm module enabled with external clock from in0 1 1 pwm module enabled with internal calibrated clock analog integrated circuit device data 34 freescale semiconductor 35xs3400 functional device operation logic commands and registers bits d5:d4 allow the mcu to select one of two analog feedback on csns output pin, as shown in table 21 . table 21. csns reporting selection temp_en (d5) csns_en (d4) csns reporting 0 0 csns tri-stated (default) x 1 current recopy of selected output (d3:2] bits) 1 0 temperature on gnd flag table 22. output current recopy selection csns1 (d3) csns0 (d2) csns reporting 0 0 hs0 (default) 0 1 hs1 1 0 hs2 1 1 hs3 the gcr register disables the over-voltage protection (d0). when this bits is [0], the over-voltage is enabled (default value). address 00111 ? calibration register (c alr) the calr register allows the mcu to calibrate internal clock, as explained in figure 12 . serial output communication (device status return data) when the cs pin is pulled low, the output register is loaded. meanwhile, the data is clocked out msb- (od15-) first as the new message data is clocked into the si pin. the first sixteen bits of data clocking out of the so, and following a cs transition, is dependent upon the previously written spi word. any bits clocked out of the serial output (so) pin after the first 16 bits will be representa tive of the initial message bits clocked into the si pin since the cs pin first transitioned to a logic [0]. this feature is useful for daisy-cha ining devices as well as message verification. a valid message length is determined following a cs transition of [0] to [1]. if there is a valid message length, the data is latched into the appropriate registers. a valid message length is a multiple of 16 bits. at this time, the so pi n is tri-stated and the fault status register is now able to accept new fault status information. so data will represent information ranging from fault statu s to register contents, us er selected by writing to the statr bits od4, od3, od2, od1, and od0. the value of the previous bits soa4 and soa3 will determine which output the so information applies to for the registers which are output specific; viz., fault, pwmr, confr0, confr1 and ocr registers. note that the so data will continue to reflect the in formation for each output (depending on the previous soa4, soa3 state) that was se lected during the most recent statr write until changed with an updated statr write. the output status register corre ctly reflects the status of the statr-selected register data at the time that the cs is pulled to a logic [0] during spi communicat ion , and/or for the period of time since the last valid spi communication, with the following exception: ?the previous spi communication was determined to be in valid. in this case, the status will be reported as though the invalid spi communication never occurred. ?the vpwr voltage is below 4.0 v, the status must be ig nored by the mcu. serial output bit assignment the 16 bits of serial output data depend on the previous seria l input message, as explained in the following paragraphs. table 23 , summarizes so retu rned data for bits od15 : od0. ? bit od15 is the msb; it re flects the state of the watchdog bit from the previously clocked-in message. ? bits od14:od10 reflect the state of the bits soa4 : soa0 from the previously clocked in message. ? bit od9 is set to logic [1] in normal mode (nm). ? the contents of bits od8 : od0 depend on bits d4 : d0 from the most recent statr command soa4 : soa0 as expl ained in the paragraphs following table 23 .
table 23. serial output bit map description previous statr so returned data s o a4 s o a3 s o a2 s o a1 s o a0 od 15 od 14 od 13 od 12 od 11 od 10 od 9 od8 od7 od6 od5 od4 od3 od2 od1 od0 statr _s a 1 a 0 0 0 0 wdi n soa 4 soa 3 soa 2 soa 1 soa 0 nm por uv ov olon_ s oloff _s os_s ot_s sc_s oc_s pwmr_ s a 1 a 0 0 0 1 wdi n soa 4 soa 3 soa 2 soa 1 soa 0 nm 0 on_s pwm6_ s pwm5_ s pwm4_ s pwm3_s pwm2_s pwm1_s pwm0_s confr 0_s a 1 a 0 0 1 0 wdi n soa 4 soa 3 soa 2 soa 1 soa 0 nm x x x dir_dis _s sr1_s sr0_s delay2_s delay1_s delay0_s confr 1_s a 1 a 0 0 1 1 wdi n soa 4 soa 3 soa 2 soa 1 soa 0 nm x x retry_ unlimite d_s retry_d is_s os_dis _s olon_dis_s oloff_dis_s olled_en _s csns_rati o_s ocr_s a 1 a 0 1 0 0 wdi n soa 4 soa 3 soa 2 soa 1 soa 0 nm x bc1_ s bc0_s oc1_s oc0_s ochi_s oclo1_s oclo0_s oc_mode _s gcr 0 0 1 0 1 wdi n soa 4 soa 3 soa 2 soa 1 soa 0 nm vdd_ fail_ en pwm _en clock _sel temp_ en csns_ en csns1 csns0 x ov_dis diagr0 0 0 1 1 1 wdi n soa 4 soa 3 soa 2 soa 1 soa 0 nm x x x x x x clock_fail cal_fail otw diagr1 0 1 1 1 1 wdi n soa 4 soa 3 soa 2 soa 1 soa 0 nm x x x x in3 in2 in1 in0 wd_en diagr2 1 0 1 1 1 wdi n soa 4 soa 3 soa 2 soa 1 soa 0 nm x x x x x x 1 x x registe r state after rst =0 or v dd(fai l) or v suppl y(por) conditi on n/ a n/ a n/ a n/ a n/ a 0 0 0 0 0 0 0 x 0 0 0 0 0 0 0 0 s = output selection with the bits a 1 a 0 as defined in table 12 analog integrated circuit device data freescale semiconductor 35 35xs3400 functional device operation logic commands and registers previous address soa4 : soa0 = a 1 a 0 000 (statr_s) the returned data od8 reports logic [1] in case of previous power on reset condition (v supply(por) ). this bit is only reset by a read operation. bits od7: od0 reflect the current state of the fault register (flt r) corresponding to the output previously selected with the bits soa4:soa3 = a 1 a 0 ( table 23 ). ? oc_s: over-current fault detection for a selected output, ? sc_s: severe short-circuit f aul t detection for a selected output, ? os_s: output shorted to vpwr fault detection for a selected output, ? oloff_s: openload in off state fault detection for a selected output, ? olon_s: openload in on state fault detection (depending on current level threshold: bulb or led) for a selected output, ? ov: over-voltage fault detection, ? uv: under-voltage fault detection ? por: power on reset detection. the fs pin reports all faults. for latched faults, this pin is reset by a new switch off command (toggling fault_control signal).
analog integrated circuit device data 36 freescale semiconductor 35xs3400 functional device operation logic commands and registers previous address soa4 : soa0 = a 1 a 0 001 (pwmr_s) the returned data contains the programmed values in the pwmr register for the output selected with a 1 a 0 . previous address soa4 : soa0 = a 1 a 0 010 (confr0_s) the returned data contains the programmed values in the confr0 register for the output selected with a 1 a 0 . previous address soa4 : soa0 = a 1 a 0 011 (confr1_s) the returned data contains the programmed values in the confr1 register for the output selected with a 1 a 0 . previous address soa4 : soa0 = a 1 a 0 100 (ocr_s) the returned data contains the programmed values in the ocr register for the output selected with a 1 a 0 . previous address soa4 : soa0 = 00101 (gcr) the returned data contains the programmed values in the gcr register. previous address soa4 : soa0 = 00111 (d iagr0) the returned data od2 reports logic [1] in case of pwm clock on in0 pin is out of specified frequency range. the returned data od1 reports logic [1] in case of calib ration failure. the returned data od0 reports logic [1] in case of over- te mperature prewarni ng (temperature of gnd flag is above t otwar ). previous address soa4 : soa0 = 01111 (d iagr1) the returned data od4: od1 report in real time the state of the direct input in[3:0]. the od0 indicates if the watchdog is enabled (set to logic [1]) or not (se t to logic [0]). od4:od1 report the output state in case of fail-safe state due to watchdog time-out as explained in the following table 24 . table 24. watchdog activation report wd_en (od0) 0 disabled 1 enabled previous address soa4 : soa0 = 10111 (d iagr2) the returned data is the product id. bits od2:od0 are set to 1xx for protected quad 35 m high side switches. default device configuration the default device configuration is explained below: ? hs output is commanded by corresponding in input or on bi t through spi. the medium slew-rate is used, ? hs output is fully protected by t he severe short-circuit protection, the under-voltage, and the over-temperature protection. the auto-retry feature is enabled, ? open-load in on and off state and hs shorted to vpwr de tections are available, ? no current recopy and no analog temperature feedback active, ? over-voltage protection is enabled, ? so reporting fault status from hs0, ? vdd failure detection is disabled.
analog integrated circuit device data freescale semiconductor 37 35xs3400 typical applications typical applications the following figure shows a typical automotive lighting application (only one vehicle corner) using an external pwm clock from the main mcu. a redundancy circuitry has been implemented to substitute li ght control (from mcu to watchdog) in case of a fail-safe condition. it is recommended to locate a 22 nf decoupling capacitor to the module connector. 35xs3400 v dd v dd v pwr gnd mcu voltage regulator v pwr 100nf hs2 hs0 hs1 hs3 vpwr vdd wake fs in0 in2 in3 sclk cs si so fsi rst in1 100nf i/o i/o sclk cs si so 10k 10k 10k 10k 10k 10k load 0 load 1 csns a/d v dd v dd v pwr v dd 22nf 22nf load 2 22nf load 3 22nf 22nf 10k watchdog direct light commands (pedal, comodo,...) vpwr ignition switch 100nf 10f 100nf 10f 100nf 4.7k 10k 10k 10k 10k
analog integrated circuit device data 38 freescale semiconductor 35xs3400 packaging soldering information packaging soldering information the 35xs3400 is packaged in a surface mount power package intended to be soldered directly on the printed circuit board. the cpna code was qualified in accordance with jedec standards j-std-020c sn-pb reflow profile. the maximum peak temperature during the soldering process should not exceed 245 for 10 seconds maximum duration. the dpna code was qualified in accordance with jedec standards j-std-020c pb-free reflow profile. the maximum peak temperature during the soldering process should not exceed 260 for 40 seconds maximum duration. the an2469 provides guidelines for printed circuit board design and assembly.
analog integrated circuit device data freescale semiconductor 39 35xs3400 packaging package dimensions package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using the 98arl10596d listed below. pna suffix 24-pin pqfn nonleaded package 98arl10596d issue d
pna suffix 24-pin pqfn nonleaded package 98arl10596d issue d analog integrated circuit device data 40 freescale semiconductor 35xs3400 packaging package dimensions
pna suffix 24-pin pqfn nonleaded package 98arl10596d issue d analog integrated circuit device data freescale semiconductor 41 35xs3400 packaging package dimensions
pna suffix 24-pin pqfn nonleaded package 98arl10596d issue d analog integrated circuit device data 42 freescale semiconductor 35xs3400 packaging package dimensions
24-pin pqfn 35xs3400pna pna suffix (pb-free) 98arl10596d 24-pin pqfn (12 x 12) note for package dimensions, refer to the 35xs3400 data sheet. analog integrated circuit device data freescale semiconductor 43 35xs3400 additional documentation thermal addendum (rev 1.0) additional documentation thermal addendum (rev 1.0) introduction this thermal addendum is provided as a su pplement to the 35xs3400 technical data sheet. the addendum provides thermal performance information that ma y be critical in the desig n and development of system applications. all electrical, application and packaging information is provided in the data sheet. package and thermal considerations this 35xs3400 is a dual die package. there are two heat sources in the packag e independently heating with p 1 and p 2 . this results in two junction temperatures, t j1 and t j2 , and a thermal resistance matrix with r jamn . for m, n = 1, r ja11 is the thermal resistance from junction 1 to the reference temperature while only heat source 1 is heating with p 1 . for m = 1, n = 2, r ja12 is the thermal resistance from junction 1 to the reference temperature while heat source 2 is heating with p 2 . this applies to r j21 and r j22 , respectively. the stated values are solely for a thermal performance comparison of one package to another in a standardized environment. this meth odology is not meant to and will not predict the performance of a package in an application- specific environment. stated values were obtained by measur ement and simulation according to the standards listed below. standards thermal resistance 1 = power chip, 2 = logic chip [c/w] m = 1, n = 1 m = 1, n = 2 m = 2, n = 1 m = 2, n = 2 27.35 18.40 35.25 14.53 6.64 23.69 47.63 37.21 53.61 1.48 0.00 0.95 notes: 1. per jedec jesd51-2 at natural convection, still air cond ition. 2. 2s2p thermal test board per jedec jesd51-7and jesd51-5. 3. per jedec jesd51-8, with the board temperature on the cente r trace near the power outputs. 4. single layer thermal test board per jedec jesd51-3 and jesd51- 5. 5. thermal resistance between the die junction and the expo sed pad, ?infinite? heat sink attached to exposed pad. figure 14. detail of copper traces under device with th ermal vias t j1 t j2 = r ja11 r ja21 r ja12 r ja22 . p 1 p 2 table 25. thermal pe rformance comparison r ja mn (1)(2) r jb mn (2)(3) r ja mn (1)(4) r jc mn (5) 0.2mm 0.2mm 0.5mm dia.
76.2mm 114.3mm analog integrated circuit device data 44 freescale semiconductor 35xs3400 additional documentation thermal addendum (rev 1.0) figure 15. 1s jedec thermal test board layout 76.2mm 114.3mm figure 16. 2s2p jedec thermal test board (r ed - top layer, yellow - two buried layers) mc35xs3400 pin connections 24 pin pqfn (12 x 12) 0.9mm pitch 12.0mm x 12.0mm body transparent top view 13 24 12 10 9 8 7 6 5 4 3 2 1 11 23 22 19 20 21 16 17 18 15 14 so gnd hs3 hs1 nc hs0 hs2 gnd fsi vdd si sclk cs rst wake fs in3 in2 nc in1 in0 csns gnd vpwr figure 17. pin connections
analog integrated circuit device data freescale semiconductor 45 35xs3400 additional documentation thermal addendum (rev 1.0) device on thermal test board material: single layer printed circuit board fr4, 1.6 mm thickness cu traces, 0.07 mm thickness cu buried traces thickness 0.03 5 mm outline: 76.2 mm x 114.3 mm board area, in cluding edge connector for thermal testing, 74 mm x 74 mm buried l ayers area area a : cu heat-spreading areas on board surface ambient conditions: natural convection, still air 25.00 30.00 35.00 40.00 45.00 50.00 55.00 60.00 65.00 0 100 200 300 400 500 600 heat spreading area [sqmm] thermal resistance [k/w] rja11 rja12=rja21 rja22 r ja is the thermal resistance between die junction and ambient air. this device is a dual die package. index m indicates the die that is heated. index n refers to the number of the die where the junction temperature is sensed. figure 18. steady state thermal resistance in dependence on heat spreading area; 1 s jedec thermal test board with spreading areas table 26. thermal resistance performance thermal resistance area a (mm 2 ) 1 = power chip, 2 = logic chip (c/w) m = 1, n = 1 m = 1, n = 2 m = 2, n = 1 m = 2, n = 2 r ja mn 0 47.63 37.21 53.61 150 42.82 33.14 51.06 300 41.23 31.84 50.36 450 40.07 30.90 49.26 600 39.24 30.14 48.57
0.1 1 10 100 0.000001 0.0001 0.01 1 100 10000 time[s] thermal resistance [k/w] rja11 rja12 rja22 analog integrated circuit device data 46 freescale semiconductor 35xs3400 additional documentation thermal addendum (rev 1.0) figure 19. transient thermal 1w step response; device on 1s jedec standard thermal test board with heat spreading areas 600 sq. mm 0.1 1 10 100 0.000001 0.0001 0.01 1 100 10000 time [s] thermal resistance [k/w] rja11 rja12 rja22 figure 20. transient thermal 1w step response; device on 2s2p jedec standard thermal test board
analog integrated circuit device data freescale semiconductor 47 35xs3400 revision history revision history revision date description of changes 4.0 9/2008 5.0 10/2008 6.0 7/2009 7.0 10/2009 8.0 1/2011 ? initial release ? changed maximum rating for output source-to-drain on resistance in static electric al characteristics table on page 7. ? added explanation for recovering to sleep mode on page 22. ? added mc35xs3400dpna part number. the ?d? version has different soldering limits. ? corrected minor formatting ? separated definitions for the 35xs3400c and 35xs3400d in the static and dynamic tables ? table 23, serial output bit map description : (diagr2 register): od1=x (instead of 0) and od0=x (instead of 0) ? previous address soa4 : soa0 = 10111 (diagr2) on page 36 : bits od2:od0 are set to 1xx (instead of 100) for protected..
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